1. Field of the Invention
The present invention relates to a video signal conversion device. More particularly, the present invention relates to a video signal conversion device for converting a non-interlaced video signal from a computer, or the like, to an interlaced video signal for television, which minimizes the number of line buffer units required and reduces the flicker and bleeding. The bleeding refers to a noise in the form of a vertical line which is not supposed to be in the original image.
2. Description of the Related Art
A video signal output from a computer device, or the like, is a signal which is not interlaced (hereinafter, referred to as a "non-interlaced" signal). In order for a computer signal to be used for television, the computer signal has to be converted to an interlaced signal. The conversion involves a process of dividing a non-interlaced input frame into two field frames, thus requiring two memories; one for reducing by one-half the vertical resolution and another for altering the horizontal synchronization frequency.
In particular, the above-described process (the non-interlaced-to-interlaced conversion process) may be performed on RGB signals, which are then subjected to a signal conversion process, or the input RGB signals may first be converted to one luminance signal and two color-difference signals. In either case, the device has to be capable of storing three data values (i.e., one luminance signal and two color-difference signals) at a time.
A conventional video signal conversion device, as illustrated in FIG. 22A, requires three line buffer units for reducing by one-half the vertical resolution, and three other line buffer units for altering the horizontal synchronization frequency.
In non-interlaced/interlaced conversion, the cycle at which one interlaced frame is displayed is 1/2 the cycle at which one non-interlaced frame is displayed, whereby it is likely for a flicker noise to occur where the luminance changes greatly in the vertical direction.
Flicker is reduced typically by removing vertical high-frequency components. This is realized by multiplying several lines above and below the displayed line by appropriate weighting coefficients and averaging them. In order to perform such a process for successively-input non-interlaced signals, it is required to provide a number of line buffers for storing data values of a number of lines used in calculating an average value (the number of lines used in the averaging process is referred to as the "number of taps"). Normally, the average calculation requires a number of line buffers one less than the number of taps. Assuming that the number of taps is n, the number of line buffers required can be obtained by multiplying the number of line buffers required for the average calculation for one route by the total number of routes (e.g., 3), and by adding to the multiplication result the number (e.g., 3) of line buffers required for altering the horizontal synchronization frequency. Thus, (the number of line buffers required)=(n-1).times.3+3=3n.
FIG. 22B illustrates signal timing diagrams at points a, b, c and d in the video signal conversion device of FIG. 22A. During period I, data of the first line is input and stored in the line buffer for vertical resolution conversion and flicker reduction. During period II, as data of the second line is input, the data of the first line which has been stored in the line buffer is read out, and the average value of the data of the first line and the data of the second line is calculated. The calculation result is then written in the line buffer for horizontal synchronization frequency conversion. During periods II and III, the calculation result is read out in synchronization with the horizontal synchronization frequency on the output side, which is 1/2 the frequency provided on the input side.
Japanese Laid-open Publication No. 6-83299 discloses a 3-tap scan conversion circuit, which is illustrated in FIG. 23.
For a 3-tap scan conversion circuit which performs a flicker reduction process, the line buffers for vertical resolution conversion and flicker reduction are not separate from the line buffers used for horizontal synchronization frequency conversion. Still, the scan conversion circuit requires 3.times.3=9 line buffers.
As described above, the conventional non-interlaced/interlaced conversion requires 3n line buffers for performing an n-tap flicker reduction process. For example, the video signal conversion device illustrated in FIG. 22A must have 6 line buffers for performing a 2-tap flicker reduction process. As the number of memories increase, the size (and thus the cost and power consumption) of the video signal conversion device increases accordingly.